As technology requirements continue to become more stringent, integrated circuit devices are being developed with increasingly higher levels of integration. Accordingly, the features formed on semiconductor wafers are being scaled smaller and smaller. In addition to the size of the features becoming smaller, space between the features is being scaled at an astounding pace. In some operations, the space between features is actually more difficult to accurately create than the feature itself. This is especially true for xe2x80x9cshrinksxe2x80x9d, or foundry technologies where silicon real estate is as important as, or more important than speed or device parameters. The following table illustrates design rules for various CMOS technologies.
As can be seen from the above, the features and space between the features continues to shrink as new technologies are developed. When using conventional photolithographic processes, the lateral separation distance between conductive or other elements at the same processing level, such as gates and word lines, of integrated circuits is generally limited to the minimum processing dimension permitted by the photolithographic process used. Advanced chemically amplified photoresists have significantly extended the life of current photo tools. Lines less than 0.18xcexc wide can now reliably be resolved. Coupling these advanced photoresists with etches which impart a negative etch bias, that is, they shrink the lines, results in a significant margin for resolving very small features. For technologies such as 0.25xcexc Foundry shrink resolving the line of 0.24xcexc is not difficult using these techniques. However, printing the space of 0.30xcexc without stringers between features maintaining a good resist profile becomes difficult.
Resist stringers may be transferred to the substrate when etching a subsequent polysilicon layer deposited over a device feature. The stringers can detrimentally short adjacent polysilicon lines formed from this polysilicon layer.
U.S. Pat. No. 5,776,836 Sandhu describes a method for defining features smaller than a resolution limit of a photolithography system. A first mask layer is formed over a substrate. The first mask layer is patterned by standard techniques with a feature size at or near the resolution limit of the system being used. A second mask layer then is deposited over the substrate. The second mask is formed with the substrate arranged at an angle to the direction of deposition, such that the first mask acts as a shield and prevent the second mask from being formed on parts of the first mask. The second mask is thus only deposited on a portion of the first mask and leaves a pattern with a feature size smaller than the smallest feature that can be printed. Arranging the substrate at an angle and depositing the second mask using the first mask as a shield is a complicated procedure and does not always result in a clear pattern being formed.
Thus, there is a need for a simple and reliable method to create spaces or features smaller than those allowed by a given lithographic process.
The present invention provides a method to define and tailor process limited lithographic features. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.
In a method according to another embodiment of the invention, a first mask is formed on a layer. The first mask is patterned into at least two portions defining spaces therebetween. Spacers are formed on sidewalls of the patterned first mask thereby reducing a dimension of the spaces. A layer is then etched using the first mask and spacers as a hard mask.